RVC: a mechanism for time-analyzable real-time processors with faulty caches

Authors:
Jaume Abella;Eduardo Quiñones;Francisco J. Cazorla;Yanos Sazeides;Mateo Valero
Affiliations:
Barcelona Supercomputing Center (BSC-CNS);Barcelona Supercomputing Center (BSC-CNS);Instituto de Investigación en Inteligencia Artificial (IIIA-CSIC);University of Cyprus (UCY);Universitat Politecnica de Catalunya (UPC)
Venue:
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Year:
2011

Citing 17
Cited 0

Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors

IEEE Transactions on Computers
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Performance Implications of Tolerating Cache Faults

IEEE Transactions on Computers
Tolerating Hard Faults in Microprocessor Array Structures

DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology

VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Impact of Parameter Variations on Circuits and Microarchitecture

IEEE Micro
Performance of Graceful Degradation for Cache Faults

ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology

DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches

RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches

RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Evaluating the effects of cache redundancy on profit

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Tolerating process variations in large, set-associative caches: The buddy cache

ACM Transactions on Architecture and Code Optimization (TACO)
Hardware support for WCET analysis of hard real-time multicore systems

Proceedings of the 36th annual international symposium on Computer architecture
Error-correcting codes for semiconductor memory applications: a state-of-the-art review

IBM Journal of Research and Development
Low Vccmin fault-tolerant cache with highly predictable performance

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
The split register file

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime embedded systems non time-analyzable or worstcase execution time (WCET) estimations unacceptably large. This paper proposes a mechanism to tolerate faulty bits in caches while still providing safe and tight WCET. Our solution is based on adapting structures such as the victim cache, cache eviction buffers or miss state handle registers to serve as replacement for faulty cache storage. We show how modest modifications in the hardware help providing safe and tight WCET on the face of permanent faulty bits with negligible impact in power and performance.