A novel cache architecture with enhanced performance and security
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Tolerating process variations in large, set-associative caches: The buddy cache
ACM Transactions on Architecture and Code Optimization (TACO)
The salvage cache: a fault-tolerant cache architecture for next-generation memory technologies
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
A scalable circuit-architecture co-design to improve memory yield for high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
Proceedings of the 48th Design Automation Conference
Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Breaking the energy barrier in fault-tolerant caches for multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 0.00 |
In sub-90nm technologies, more frequent hard faults pose a serious burden o n processor design and yield control. I n addition t o manufacturing-time chip repair schemes, microarchitectural techniques t o make processor components resilient t o hard faults will become increasingly important. This paper considers defects in cache memory and studies their impact on program performance using a fault degradable cache model.We first describe how defects at the circuit level in cache manifest themselves at the microarchitecture level. We then examine several strategies for masking faults, by disabling faulty resources, such as lines, sets, ways, ports, or even the whole cache. We also propose an efficient cache set remapping scheme t o recover lost performance due to failed sets. Using a new simulation tool, called CAFE, we study how the cache faults impact program performance under the various masking schemes.