A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance of Graceful Degradation for Cache Faults
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Fine-Grained Fault Tolerance for Process Variation-Aware Caches
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Voltage scaling can be applied to cache memories to reduce their energy consumptions. However, reduced supply voltage to the cache memories increases defective SRAM cells due to process variations, which will decrease their yields and performance nullifying the benefits of voltage scaling. To mitigate this problem, we propose a fault buffer-based scheme for L1 caches. Faults are identified and isolated at the granularity of individual words in the L1 caches. Actively used faulty cache words are allocated in the fault buffers dynamically. The fault buffers are organized as multiple banks for low cost implementation and can be reconfigured dynamically to reflect varying performance demands of programs. This dynamic scheme is shown to be more energy- and area-efficient than, and to be performing comparably to the previously proposed static schemes.