DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips

  • Authors:

  • Andrew DeOrio;Kostantinos Aisopos;Valeria Bertacco;Li-Shiuan Peh

  • Affiliations:

  • University of Michigan, Ann Arbor, MI;Princeton University, Princeton, NJ and Massachusetts Institute of Technology, Cambridge, MA;University of Michigan, Ann Arbor, MI;Massachusetts Institute of Technology, Cambridge, MA

  • Venue:
  • Proceedings of the 48th Design Automation Conference
  • Year:
  • 2011

Quantified Score

Hi-index 0.00

Visualization

Abstract

As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, enabling the design of highly integrated chips with many cores and a complex interconnect fabric, often a network on chip (NoC). Particularly problematic is the case when the accumulation of permanent hardware faults leads to disconnected cores in the system. In order to maintain correct system operation, it is necessary to salvage the data from these isolated nodes. In this work, we introduce a recovery mechanism targeting precisely this issue: DRAIN (Distributed Recovery Architecture for Inaccessible Nodes) provides system-level recovery from permanent failures. When an error disconnects a node from the network, DRAIN uses emergency links to transfer architectural state and cached data from disconnected nodes to nearby connected caches. DRAIN incurs zero performance penalty during normal operation, and is compatible with any cache coherence protocol, interconnect topology or routing protocol. Experimental results show that DRAIN is able to provide complete state recovery within several milliseconds, on average, for a 1GHz 64-node CMP at an area overhead of only a few thousand gates.