A novel cache architecture with enhanced performance and security

Authors:
Zhenghong Wang;Ruby B. Lee
Affiliations:
Princeton Architecture Laboratory for Multimedia and Security (PALMS), Department of Electrical Engineering, Princeton University, NJ 08544, USA;Princeton Architecture Laboratory for Multimedia and Security (PALMS), Department of Electrical Engineering, Princeton University, NJ 08544, USA
Venue:
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Year:
2008

Citing 15
Cited 16

Cache performance of operating system and multiprogramming workloads

ACM Transactions on Computer Systems (TOCS)
Column-associative caches: a technique for reducing the miss rate of direct-mapped caches

ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Capturing dynamic memory reference behavior with adaptive cache topology

Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Way-predicting set-associative cache for high performance and low energy consumption

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Reconfigurable caches and their application to media processing

Proceedings of the 27th annual international symposium on Computer architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
True Random Number Generator Embedded in Reconfigurable Hardware

CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
PADded Cache: A New Fault-Tolerance Technique for Cache Memories

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

ACM-SE 42 Proceedings of the 42nd annual Southeast regional conference
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches

Proceedings of the 33rd annual international symposium on Computer Architecture
New cache designs for thwarting software cache-based side channel attacks

Proceedings of the 34th annual international symposium on Computer architecture
Performance of Graceful Degradation for Cache Faults

ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Working with process variation aware caches

Proceedings of the conference on Design, automation and test in Europe
Cache-collision timing attacks against AES

CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems

NoHype: virtualized cloud infrastructure without the virtualization

Proceedings of the 37th annual international symposium on Computer architecture
A predictive model for cache-based side channels in multicore and multithreaded microprocessors

MMM-ACNS'10 Proceedings of the 5th international conference on Mathematical methods, models and architectures for computer network security
Cache index-aware memory allocation

Proceedings of the international symposium on Memory management
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks

ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Architectural support for hypervisor-secure virtualization

ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Side-channel vulnerability factor: a metric for measuring information leakage

Proceedings of the 39th Annual International Symposium on Computer Architecture
TimeWarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks

Proceedings of the 39th Annual International Symposium on Computer Architecture
Inspection resistant memory: architectural support for security from physical examination

Proceedings of the 39th Annual International Symposium on Computer Architecture
Whispers in the hyper-space: high-speed covert channel attacks in the cloud

Security'12 Proceedings of the 21st USENIX conference on Security symposium
STEALTHMEM: system-level protection against cache-based side channel attacks in the cloud

Security'12 Proceedings of the 21st USENIX conference on Security symposium
Position paper: Sapper -- a language for provable hardware policy enforcement

Proceedings of the Eighth ACM SIGPLAN workshop on Programming languages and analysis for security
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip

Proceedings of the 40th Annual International Symposium on Computer Architecture
Side channel vulnerability metrics: the promise and the pitfalls

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
Security testing of a secure cache design

Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
Düppel: retrofitting commodity operating systems to mitigate cache side channels in the cloud

Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
Sapper: a language for hardware-level security policy enforcement

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent findings on efficient attacks based on information leakage in caches have also brought the security issue up front. Design for security introduces even more restrictions and typically leads to significant performance degradation. This paper presents a novel cache architecture that can simultaneously achieve the above goals. Specifically, cache miss rates are reduced with dynamic remapping and longer cache indices, access-time overhead overcome with astute low-level circuit design, and information leakage thwarted by a security-aware cache replacement algorithm together with the performance enhancing mechanisms. We present both theoretical analysis and experimental results, using the SPEC2000 suite to evaluate the cache miss behavior, and CACTI and HSPICE to validate the circuit design. Our results show that the proposed cache architecture has low miss rates comparable to a highly associative cache and short access times and power efficiency close to that of a direct-mapped cache. At the same time it can thwart cache-based software side-channel attacks, providing both legacy and security-enhanced software a much higher degree of security. Additional benefits that the proposed cache architecture can bring, like fault tolerance and hot-spot mitigation, are also discussed briefly.