A predictive model for cache-based side channels in multicore and multithreaded microprocessors

Authors:
Leonid Domnitser;Nael Abu-Ghazaleh;Dmitry Ponomarev
Affiliations:
Computer Science Department, State University of New York at Binghamton, Binghamton, NY;Computer Science Department, State University of New York at Binghamton, Binghamton, NY;Computer Science Department, State University of New York at Binghamton, Binghamton, NY
Venue:
MMM-ACNS'10 Proceedings of the 5th international conference on Mathematical methods, models and architectures for computer network security
Year:
2010

Citing 12
Cited 1

Linear cryptanalysis method for DES cipher

EUROCRYPT '93 Workshop on the theory and application of cryptographic techniques on Advances in cryptology
Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The Design of Rijndael

The Design of Rijndael
DES and Differential Power Analysis (The "Duplication" Method)

CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Random Register Renaming to Foil DPA

CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
New cache designs for thwarting software cache-based side channel attacks

Proceedings of the 34th annual international symposium on Computer architecture
An information-theoretic model for adaptive side-channel attacks

Proceedings of the 14th ACM conference on Computer and communications security
A novel cache architecture with enhanced performance and security

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks

EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
Efficient Cache Attacks on AES, and Countermeasures

Journal of Cryptology
Towards security limits in side-channel attacks

CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Cache-collision timing attacks against AES

CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems

Side-channel vulnerability factor: a metric for measuring information leakage

Proceedings of the 39th Annual International Symposium on Computer Architecture

Quantified Score

Hi-index	0.00

Visualization

Abstract

A side channel is an information channel that unintentionally communicates information about a program as a side effect of the implementation. Recent studies have illustrated the use of shared caches as side channels to extract private keys from computationally secure cryptographic applications. The cache side channel is imperfect in the sense that the attacker's ability to detect cache leakage of critical data is limited by the timing issues. Moreover, some detected leakages are due to non-critical data. Thus, it is difficult to assess the degree of vulnerability given the imperfect nature of the side-channel. Similarly, when solutions that further degrade the quality of the channel, but do not necessarily close it completely, are employed, it is difficult to evaluate their effectiveness. To address this need, this paper proposes a mathematical model to evaluate the expected leakage in a cache as a function of the cache parameters and the victim application behavior. We use simulation to quantify these parameters for typical attack scenarios to validate the model. We demonstrate that the proposed model accurately estimates side channel leakage for for AES and Blowfish encryption and decryption on a variety of cache configurations.