Rescue: A Microarchitecture for Testability and Defect Tolerance
Proceedings of the 32nd annual international symposium on Computer Architecture
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
Online diagnosis of hard faults in microprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Low-cost protection for SER upsets and silicon defects
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
The StageNet fabric for constructing resilient multicore systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Architectural core salvaging in a multi-core processor for hard-error tolerance
Proceedings of the 36th annual international symposium on Computer architecture
Necromancer: enhancing system throughput by animating dead cores
Proceedings of the 37th annual international symposium on Computer architecture
Scalable thread scheduling and global power management for heterogeneous many-core architectures
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Combating Aging with the Colt Duty Cycle Equalizer
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
ROSY: recovering processor and memory systems from hard errors
ACM SIGOPS Operating Systems Review
Viper: virtual pipelines for enhanced reliability
Proceedings of the 39th Annual International Symposium on Computer Architecture
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Flicker: a dynamically adaptive architecture for power limited multicore systems
Proceedings of the 40th Annual International Symposium on Computer Architecture
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
A column parity based fault detection mechanism for FIFO buffers
Integration, the VLSI Journal
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In this paper, we present a hardware technique, calledSelf-Repairing Array Structures (SRAS), for maskinghard faults in microprocessor array structures, such asthe reorder buffer and branch history table. SRAS maskserrors that could otherwise lead to slow system recoveries.To detect row errors, every write to a row is mirroredto a dedicated "check row." We then read out boththe written row and check row and compare theirresults. To correct errors, SRAS maps out faulty arrayrows with a level of indirection.