The StageNet fabric for constructing resilient multicore systems

  • Authors:

  • Shantanu Gupta;Shuguang Feng;Amin Ansari;Jason Blome;Scott Mahlke

  • Affiliations:

  • Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA;Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA

  • Venue:
  • Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing operating temperatures and current densities. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Consequently, high reliability and fault tolerance, which have traditionally been subjects of interest for high-end server markets, are now getting emphasis in the mainstream desktop and embedded systems space. The popular solution for this has been the use of redundancy at a coarse granularity, such as dual/triple modular redundancy. In this work, we challenge the practice of coarse-granularity redundancy by identifying its inability to scale to high failure rate scenarios and investigating the advantages of finer-grained configurations. To this end, this paper presents and evaluates a highly reconfigurable multicore architecture, named StageNet (SN), that is designed with reliability as its first class design criteria. SN relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of a chip, gracefully degrading performance towards the end of life. Our results show that the proposed SN architecture can perform nearly 50% more cumulative work compared to a traditional multicore.