Integrating superscalar processor components to implement register caching

Authors:
Matthew Postiff;David Greene;Steven Raasch;Trevor Mudge
Affiliations:
Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI;Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI;Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI;Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI
Venue:
ICS '01 Proceedings of the 15th international conference on Supercomputing
Year:
2001

Citing 15
Cited 14

Hierarchical registers for scientific computers

ICS '88 Proceedings of the 2nd international conference on Supercomputing
System V application binary interface (3rd ed.)

System V application binary interface (3rd ed.)
Exploiting short-lived variables in superscalar processors

Proceedings of the 28th annual international symposium on Microarchitecture
Register renaming and dynamic speculation: an alternative approach

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
Exploiting dead value information

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Delaying physical register allocation through virtual-physical registers

Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems
Multiple-banked register file architectures

Proceedings of the 27th annual international symposium on Computer architecture
The MIPS R10000 Superscalar Microprocessor

IEEE Micro
The Design Space of Register Renaming Techniques

IEEE Micro
Caching processor general registers

ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
RISC I: A Reduced Instruction Set VLSI Computer

ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Virtual-Physical Registers

HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance

Compiler and microarchitecture mechanisms for exploiting registers to improve memory performance
Virtual Registers

HIPC '97 Proceedings of the Fourth International Conference on High-Performance Computing

Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks

SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Dynamic addressing memory arrays with physical locality

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Optimization for the Intel® Itanium® architecture register stack

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Exploiting Value Locality in Physical Register Files

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Physical Register Inlining

Proceedings of the 31st annual international symposium on Computer architecture
How to Fake 1000 Registers

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Compacting register file via 2-level renaming and bit-partitioning

Microprocessors & Microsystems
Reconciling performance and programmability in networking systems

Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
Exploiting virtual registers to reduce pressure on real registers

ACM Transactions on Architecture and Code Optimization (TACO)
Asymmetrically banked value-aware register files for low-energy and high-performance

Microprocessors & Microsystems
The StageNet fabric for constructing resilient multicore systems

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Energy-efficient register caching with compiler assistance

ACM Transactions on Architecture and Code Optimization (TACO)
Virtual registers: reducing register pressure without enlarging the register file

HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
2L-MuRR: a compact register renaming scheme for SMT processors

ISPA'05 Proceedings of the Third international conference on Parallel and Distributed Processing and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches are combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache for the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.