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Proceedings of the 24th annual international symposium on Computer architecture
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Proceedings of the 24th annual international symposium on Computer architecture
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The Alpha 21264 Microprocessor
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The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor
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Register File Design Considerations in Dynamically Scheduled Processors
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A Scalable Register File Architecture for Dynamically Scheduled Processors
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IEEE Transactions on Computers
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Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This paper present a novel physical register management scheme that allows for a late allocation (at the end of execution) of registers. We show that it can provide significant savings in number of registers and thus, it can significantly shorter the register file access time. The approach is based on virtual-physical registers, which we presented in a previous work, extended with a new register allocation policy. This policy consists of an on-demand allocation in order to maximize the register usage, combined with a stealing mechanism that prevents older instruction from being delayed by younger ones. This shortens the average number of cycles that each physical register is allocated, and allows for an early execution of instructions since they can obtain a physical register for its destination earlier than with the conventional scheme. Early execution is especially beneficial for branches and memory operations, since the former can be resolved earlier and the latter can prefetch their data in advance.