Implicit transactional memory in kilo-instruction multiprocessors

  • Authors:

  • Marco Galluzzi;Enrique Vallejo;Adrián Cristal;Fernando Vallejo;Ramón Beivide;Per Stenström;James E. Smith;Mateo Valero

  • Affiliations:

  • Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya;Grupo de Arquitectura de Computadores, Universidad de Cantabria;Barcelona Supercomputing Center;Grupo de Arquitectura de Computadores, Universidad de Cantabria;Grupo de Arquitectura de Computadores, Universidad de Cantabria;Dept. of Computer Science and Engineering, Chalmers University of Technology;Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison;Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya and Barcelona Supercomputing Center

  • Venue:
  • ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
  • Year:
  • 2007

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Abstract

Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of combining a number of such multi-core chips into a system. The widespread use of multiprocessor systems will make performance losses due to consistency models and synchronization styles of popular programming models even more evident than they already are. Known architectural approaches to combat these losses are generally too complex, too specialized, or not transparent to software. In this article, we introduce implicit transactional memory as a generalized architectural concept to remove unnecessary performance losses caused by consistency models and synchronization styles. We show how the concept of implicit transactions can be implemented with low complexity by leveraging the multicheckpoint mechanism of the Kilo-Instruction Processor. By relying on a general speculation substrate, this method supports even the strictest consistency model - sequential consistency - potentially as effectively as weaker models and it allows multiple threads to speculatively execute critical sections, beyond barriers and event synchronizations.