Combined performance gains of simple cache protocol extensions

  • Authors:

  • F. Dahlgren;M. Dubois;P. Stenström

  • Affiliations:

  • Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 LUND, Sweden;Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA;Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 LUND, Sweden

  • Venue:
  • ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
  • Year:
  • 1994

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Abstract

We consider three simple extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with memory accesses and include a hardware prefetching scheme, a migratory sharing optimization, and a competitive-update mechanism. Since they target different components of the read and write penalties, they can be combined effectively.Detailed architectural simulations using five benchmarks show substantial combined performance gains obtained at a modest additional hardware cost. Prefetching in combination with competitive-update is the best combination under release consistency in systems with sufficient network bandwidth. By contrast, prefetching plus the migratory sharing optimization is advantageous under sequential consistency and/or in systems with limited network bandwidth.