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ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
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ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
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Tolerating latency through software-controlled data prefetching
Tolerating latency through software-controlled data prefetching
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Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors
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We study the efficiency of previously proposed stride and sequential prefetching驴two promising hardware-based prefetching schemes to reduce read-miss penalties in shared-memory multiprocessors. Although stride accesses dominate in four out of six of the applications we study, we find that sequential prefetching does as well as and in same cases even better than stride prefetching for five applications. This is because 1) most strides are shorter than the block size (we assume 32 byte blocks), which means that sequential prefetching is as effective for these stride accesses, and 2) sequential prefetching also exploits the locality of read misses with nonstride accesses. However, since stride prefetching in general results in fewer useless prefetches, it offers the extra advantage of consuming less memory-system bandwidth.