Partially ordered epochs for thread-level speculation
Proceedings of the 2nd conference on Computing frontiers
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ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
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Optimistic concurrency for clusters via speculative locking
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
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SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Implicit transactional memory in kilo-instruction multiprocessors
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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We present a new method 驴 Speculative Lock Reordering (SLR) 驴 that enables multiple threads to concurrently and speculatively execute within a critical section. Its novel feature is to exploit that there is no a priori execution order between separate invocations of a critical section that speculatively executed threads must respect. In contrast to previously proposed speculative synchronization schemes, we show that since an execution order can be selected that removes as many data dependences as possible, SLR can expose more concurrency. Additionally, it is shown that SLR can be implemented in achip-multiprocessor by only modest extensions to already published thread-level data dependence speculation systems.