Advanced compiler optimizations for supercomputers
Communications of the ACM - Special issue on parallelism
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Delaying physical register allocation through virtual-physical registers
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
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Dynamic register renaming is a mechanism present in many high performance microprocessors of latest generation aimed at removing false dependencies from the code. Unfortunately, in many cases, this mechanism keeps busy more registers than the necessary. In this paper we introduce a novel technique, called Selective Register Renaming, in which the compiler helps the processor to save physical registers when the hardware renames registers. The paper explains the principles of this technique and shows its effects on several Livermore Kernel Loops.