A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors

Authors:
Adrián Cristal;José F. Martínez;Josep Llosa;Mateo Valero
Affiliations:
Universitat Politécnica de Catalunya, Spain;Cornell University Ithaca, NY;Universitat Politécnica de Catalunya, Spain;Universitat Politécnica de Catalunya, Spain
Venue:
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Year:
2003

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Abstract

Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. In particular, we present some of our research having such observations as a basis to deal with future resource conscious processors.