Scalable Hardware Memory Disambiguation for High-ILP Processors

Authors:
Simha Sethumadhavan;Rajagopalan Desikan;Doug Burger;Charles R. Moore;Stephen W. Keckler
Affiliations:
The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin
Venue:
IEEE Micro
Year:
2004

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Abstract

Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state proportional to the instruction window size. A new class of solutions yields an order-of-magnitude reduction in the energy required to properly order loads and stores for windows of hundreds to thousands of in-flight instructions.