Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors

  • Authors:

  • Haitham Akkary;Ravi Rajwar;Srikanth T. Srinivasan

  • Affiliations:

  • Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR

  • Venue:
  • Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
  • Year:
  • 2003

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Abstract

Large instruction window processors achieve high performance by exposing large amounts of instruction levelparallelism. However, accessing large hardware structurestypically required to buffer and process such instructionwindow sizes significantly degrade the cycle time. This paper proposes a novel Checkpoint Processing and Recovery(CPR) microarchitecture, and shows how to implement alarge instruction window processor without requiring largestructures thus permitting a high clock frequency.We focus on four critical aspects of a microarchitecture:1) scheduling instructions, 2) recovering from branch mispredicts, 3) buffering a large number of stores and forwarding data from stores to any dependent load, and 4) reclaiming physical registers. While scheduling window size isimportant, we show the performance of large instructionwindows to be more sensitive to the other three design issues. Our CPR proposal incorporates novel microarchitectural schemes for addressing these design issues-a selective checkpoint mechanism for recovering from mispredicts,a hierarchical store queue organization for fast store-loadforwarding, and an effective algorithm for aggressive physical register reclamation. Our proposals allow a processor to realize performance gains due to instruction windowsof thousands of instructions without requiring large cycle-critical hardware structures.