CRIB: consolidated rename, issue, and bypass

  • Authors:

  • Erika Gunadi;Mikko H. Lipasti

  • Affiliations:

  • Intel Corporation, Santa Clara, CA, USA;University of Wisconsin - Madison, Madison, WI, USA

  • Venue:
  • Proceedings of the 38th annual international symposium on Computer architecture
  • Year:
  • 2011

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Abstract

Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined execution lanes. This requires multiple complex structures and repeated dependency resolution, imposing a significant dynamic power overhead. This paper advocates in-place execution of instructions, a power-saving, pipeline-free approach that consolidates rename, issue, and bypass logic into one structure---the CRIB---while simultaneously eliminating the need for a multiported register file, instead storing architected state in a simple rank of latches. CRIB achieves the high IPC of an out-of-order machine while keeping the execution core clean, simple, and low power. The datapath within a CRIB structure is purely combinational, eliminating most of the clocked elements in the core while keeping a fully synchronous yet high-frequency design. Experimental results match the IPC and cycle time of a baseline out-of-order design while reducing dynamic energy consumption by more than 60% in affected structures.