Software pipelining: an effective scheduling technique for VLIW machines
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MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
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The Journal of Supercomputing - Special issue on instruction-level parallelism
The superblock: an effective technique for VLIW and superscalar compilation
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List scheduling with and without communication delays
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
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Instruction scheduling and fetch mechanisms for clustered vliw processors
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FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
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FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
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ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Compiler Support for Scalable and Efficient Memory Systems
IEEE Transactions on Computers
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ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
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Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
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Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
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FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Energy characterization of a tiled architecture processor with on-chip networks
Proceedings of the 2003 international symposium on Low power electronics and design
Cluster assignment of global values for clustered VLIW processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Increasing demand for both greater parallelism and faster clocks dictate that future generation architectures will need to decentralize their resources and eliminate primitives that require single cycle global communication. A Raw microprocessor distributes all of its resources, including instruction streams, register files, memory ports, and ALUs, over a pipelined two-dimensional mesh interconnect, and exposes them fully to the compiler. Because communication in Raw machines is distributed, compiling for instruction-level parallelism (ILP) requires both spatial instruction partitioning as well as traditional temporal instruction scheduling. In addition, the compiler must explicitly manage all communication through the interconnect, including the global synchronization required at branch points. This paper describes RAWCC, the compiler we have developed for compiling general-purpose sequential programs to the distributed Raw architecture. We present performance results that demonstrate that although Raw machines provide no mechanisms for global communication the Raw compiler can schedule to achieve speedups that scale with the number of available functional units.