Maps: a compiler-managed memory system for raw machines

  • Authors:

  • Rajeev Barua;Walter Lee;Saman Amarasinghe;Anant Agarwal

  • Affiliations:

  • M.I.T. Laboratory for Computer Science, Cambridge, MA;M.I.T. Laboratory for Computer Science, Cambridge, MA;M.I.T. Laboratory for Computer Science, Cambridge, MA;M.I.T. Laboratory for Computer Science, Cambridge, MA

  • Venue:
  • ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
  • Year:
  • 1999

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Abstract

This paper describes Maps, a compiler managed memory system for Raw architectures. Traditional processors for sequential programs maintain the abstraction of a unified memory by using a single centralized memory system. This implementation leads to the infamous "Von Neumann bottleneck," with machine performance limited by the large memory latency and limited memory bandwidth. A Raw architecture addresses this problem by taking advantage of the rapidly increasing transistor budget to move much of its memory on chip. To remove the bottleneck and complexity associated with centralized memory, Raw distributes the memory with its processing elements. Unified memory semantics are implemented jointly by the hardware and the compiler. The hardware provides a clean compiler interface to its two inter-tile interconnects: a fast, statically schedulable network and a traditional dynamic network. Maps then uses these communication mechanisms to orchestrate the memory accesses for low latency and parallelism while enforcing proper dependence. It optimizes for speed in two ways: by finding accesses that can be scheduled on the static interconnect through static promotion, and by minimizing dependence sequentialization for the remaining accesses. Static promotion is performed using equivalence class unification and modulo unrolling; memory dependences are enforced through explicit synchronization and software serial ordering. We have implemented Maps based on the SUIF infrastructure. This paper demonstrates that the exclusive use of static promotion yields roughly 20-fold speedup on 32 tiles for our regular applications and about 5-fold speedup on 16 or more tiles for our irregular applications. The paper also shows that selective use of dynamic accesses can be a useful complement to the mostly static memory system.