Memory-Aware application mapping on coarse-grained reconfigurable arrays

Authors:
Yongjoo Kim;Jongeun Lee;Aviral Shrivastava;Jonghee Yoon;Yunheung Paek
Affiliations:
School of EECS, Seoul National University, Seoul, Korea;School of ECE, Ulsan National Institute of Science and Technology, Ulsan, Korea;Compiler Microarchitecture Lab, Arizona State University;School of EECS, Seoul National University, Seoul, Korea;School of EECS, Seoul National University, Seoul, Korea
Venue:
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Year:
2010

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Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Our proposed solution achieves 62% reduction in the energy-delay product, which factors into about 47% and 28% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications, and memory parameters.