Space-time scheduling of instruction-level parallelism on a raw machine
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Architecture driven partitioning
Proceedings of the conference on Design, automation and test in Europe
Static schedluing of multiple asynchronous domains for functional verification
Proceedings of the 38th annual Design Automation Conference
Incremental reconfiguration of multi-FPGA systems
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures
IEEE Transactions on Parallel and Distributed Systems
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Static scheduling of multi-domain memories for functional verification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimization of Run-Time Reconfigurable Embedded Systems
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Parallelizing Applications into Silicon
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Functionally partitioned module-based programmable architecture for wireless base-band processing
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leveraging latency-insensitivity to ease multiple FPGA design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. However, traditional FPGA-based logic emulators have poor inter-chip communication bandwidth, commonly limiting gate utilization to less than 20%. Global routing contention mandates the use of expensive crossbar and PC-board technology in a system of otherwise low-cost commodity parts. Even with crossbar technology, current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires, and pipelining these connections at the maximum clocking frequency of the FPGA. The resulting increase in bandwidth allows effective use of low-dimension direct interconnect. The size of the FPGA array can be decreased as well, resulting in low-cost logic emulation. This paper covers major contributions of the MIT Virtual Wires project. In the context of a complete emulation system, we analyze phase-based static scheduling and routing algorithms, present virtual wires synthesis methodologies, and overview an operational prototype with 20 K-gate boards. Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45%. Theoretical analysis predicts that virtual wires emulation scales with FPGA size and average routing distance, while traditional emulation does not