Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-FPGA systems
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multi-FPGA boards(MFBs) are extensively used by the designers for logic emulation, rapid prototyping, custom computing and low volume sub-system implementation. Efficient use of an MFB does not only require a good routing topology, but also a good set of CAD tools to partition the given circuits and embed them on the MFB. Khalid et al[1] have shown that among the MFB topologies, hybrid series of architectures containing fixed FPGA-FPGA connections and programmable connections through Field Programmable Interconnect Devices(FPIDs) are better than other architectures. Programmable connections can connect different pairs of FPGAs under program control, but require additional wires, extra delays etc. compared to fixed connection. An MFB, to be used in rapid prototyping, is expected to emulate a large number of digital circuits. To accommodate the routing requirement generated by partitioning them, MFB is required to have significantly large number of programmable connections. In this paper, we have shown that an efficient embedding tool can substantially reduce the requirement of programmable connections. The paper presents an optimal as well as a fast heuristic for embedding. Our methods can work with a large class of hybrid routing topologies.