PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Board-level multiterminal net routing for FPGA-based logic emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to algorithms
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
SoC HW/SW verification and validation
Proceedings of the 16th Asia and South Pacific Design Automation Conference
FPGA-based Prototyping Methodology Manual: Best Practices in Design-for-Prototyping
FPGA-based Prototyping Methodology Manual: Best Practices in Design-for-Prototyping
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
On optimal board-level routing for FPGA-based logic emulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic emulation with virtual wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.