Linear programming and network flows (2nd ed.)
Linear programming and network flows (2nd ed.)
Field-programmable gate arrays
Field-programmable gate arrays
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
On optimal board-level routing for FPGA-based logic emulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
Circuit clustering for delay minimization under area and pin constraints
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [Varghese et al. 1993] and the Enterprise Emulation System [Maliniak 1992] manufactured by Quickturn Design Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets [Chan and Schlag 1993; Mak and Wong 1995]. We show how multiterminal nets can be handled by decomposition into two-terminal nets. We show that the multiterminal net decomposition problem can be modeled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists.