Definition and solution of the memory packing problem for field-programmable systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Placement and routing for a field programmable multi-chip module
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
On optimal board-level routing for FPGA-based logic emulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Board-level multi-terminal net routing for FPGA-based logic emulation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault emulation: a new approach to fault grading
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A reconfigurable hardware approach to network simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Board-level multiterminal net routing for FPGA-based logic emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Module generation of complex macros for logic-emulation applications
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-way FPGA partitioning by fully exploiting design hierarchy
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-terminal net routing for partial crossbar-based multi-FPGA systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient resource arbitration in reconfigurable computing environments
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Logic emulation with virtual wires
Readings in hardware/software co-design
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fast Prototyping with Co-operation of Simulation and Emulation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Multiterminal net routing for partial crossbar-based multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Hierarchical Partitioning in a Rapid Prototyping Environment
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Designing BEE: a hardware emulation engine for signal processing in low-power wireless applications
EURASIP Journal on Applied Signal Processing
The yield enhancement of field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The use of computer-aided prototyping (CAP) with the RPM Emulation System is described. RPM creates a hardware functional prototype from an ASIC or full-custom chip netlist. It reads the chip netlist and then converts the chip design gates into a prototype design. It then synthesizes the prototype design, obtaining the information it needs to configure the reprogrammable hardware, primarily with partitioning and placement and routing technology. Finally, it physically implements the prototype design by electronically configuring the reprogrammable hardware. RPM includes embedded tools for interactive debugging with access to any internal design node, and a facility for handling quick incremental changes to the design. It is argued that other techniques such as silicon prototyping and manual prototyping are not practical; silicon has a poor debugging ability, and manual prototyping cannot handle large designs. The practical benefits of CAP are discussed.