A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
The Transmogrifier-2: a 1 million gate rapid-prototyping system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel and efficient routing architecture for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
Hardware/Software Codesign and Rapid Prototyping of Embedded Systems
IEEE Design & Test
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Rapid prototyping of DSP systems: requirements and solutions
RSP '95 Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95)
Rapid-Prototyping of Embedded Systems via Reprogrammable Devices
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
A Data-Flow Oriented Co-Design for Reconfigurable Systems
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Truly Rapid Prototyping Requires High-Level Synthesis
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Emulating Large Designs on Small Reconfigurable Hardware
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Real Time Prototyping Method and a Case Study
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
System-Level Verification -- A Comparison of Approaches
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Evaluation of Various Routing Architectures for Multi-FPGA Boards
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Methodology for Architecture-Oriented Rapid Prototyping
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A Rapid Prototyping Methodology and Platform for Seamless Communication Systems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
The Journal of Supercomputing
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This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.