Demand driven simulation: BACKSIM
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
Designing BEE: a hardware emulation engine for signal processing in low-power wireless applications
EURASIP Journal on Applied Signal Processing
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Abstract: The time spent in simulation grows in an exponential form with the complexity of the circuit. Therefore, improving the simulation speed can represent a significant profit regarding the verification time. Several approaches can be used to speedup the simulation. These recent years, FPGAs have been used to develop emulators. These systems are composed of several thousands of FPGAs connected together through a programmable network. Although this approach seems very attractive in regard of the speedup, all the information included in a circuit description cannot be mapped on the emulator. In this paper, we propose a method to reproduce the timing behavior of the circuit on an emulator.