MIXS: A mixed level simulator for large digital system logic verification
DAC '80 Proceedings of the 17th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Hardware acceleration of logic simulation using a data flow microarchitecture
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Load Balancing in a Hybrid ATPG Environment
IEEE Transactions on Computers
DAC '94 Proceedings of the 31st annual Design Automation Conference
Logic simulation system using simulation processor (SP)
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fault simulation in a distributed environment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Clock even suppression algorithm of VELVET and its application to S-820 development
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A technique for distributed execution of design automation tools
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Speed up techniques of logic simulation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAL II: a mixed level hardware logic simulation system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Simulation Engines in Japan
IEEE Design & Test
Some Recent Advances in Software and Hardware Logic Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Approach to Mapping the Timing Behavior of VLSI Circuits on Emulators
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
EURO-DAC '90 Proceedings of the conference on European design automation
Using a hardware simulation engine for custom MOS structured designs
IBM Journal of Research and Development
Methodology for & results from the use of a hardware logic simulation engine for fault simulation
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
| Hi-index | 0.00 |
A special purpose hardware machine, which simulates up to one half million gates and 2M byte RAM ICs at a 5 millisecond clock speed, is described. This is accomplished with a HArdware Logic (HAL) simulator. This performance is achieved with 32 distributed special parallel processors, which utilize Block Oriented Simulation Technique. The technique promises a good cost hardware logic simulator.