HAL: A block level HArdware Logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel logic simulation on a network of workstations using parallel virtual machine
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A logic simulation engine based on a modified data flow architecture
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Design Automation Systems in Japan
IEEE Design & Test
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper describes a (special-purpose) logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices. Our system can evaluate a logic circuit containing 4 million logic primitives and 32M bytes of memory at a maximum speed of 800 million active primitive evaluations per second.This paper outlines the hardware architecture, then discusses a software system that optimizes hardware performance. It presents the results of system use and evaluates the system.