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This paper describes a mixed level hardware logic simulation system, called Hardware Logic Simulator II (HAL II). This paper first shows a HAL II simulation method. Then, it overviews HAL II hardware and software system configurations, simulation mechanism and estimates system performance. The HAL II system can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language). Finally, it discusses system applications and results. The paper also indicates that HAL II has been successfully used.