Clock even suppression algorithm of VELVET and its application to S-820 development

Authors:
Yoshio Takamine;Shunsuke Miyamoto;Shigeo Nagashima;Masayuki Miyoshi;Shun Kawabe
Affiliations:
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan;Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan;Kanagawa Works, Hitachi, Ltd., Hadano, Kanagawa 259-13, Japan;Kanagawa Works, Hitachi, Ltd., Hadano, Kanagawa 259-13, Japan
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

An advanced clock event suppression algorithm for high-speed logic simulation is described.A new signal value “Cn” and a “current clock (CC)”, which indicates the current status of clock signals, has been introduced to realize this algorithm.This algorithm suppresses about 60% of the total events, and eliminates 40% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification).Hitachi's latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.