Algorithm for vectorizing logic simulation and evaluation of “VELVET” performance

Authors:
Yoshiharu Kazama;Yoshiaki Kinoshita;Motonobu Nagafuji;Hiroshi Murayama
Affiliations:
Kanagawa Works, Hitachi Ltd., Hadano, Kanagawa 259-13, Japan;Kanagawa Works, Hitachi Ltd., Hadano, Kanagawa 259-13, Japan;Hitachi Computer Engineering Co., Ltd. Hadano, Kanagawa 259-13, Japan;Hitachi Computer Engineering Co., Ltd. Hadano, Kanagawa 259-13, Japan
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

A very large-scale logic simulation engine “VELVET” has been developed. VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and Register Transfer Level structure.VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. This paper describes how to realize such high performance, an algorithm for vectorizing the simulation and performance.