Fault-test analysis techniques based on logic simulation
DAC '72 Proceedings of the 9th Design Automation Workshop
ACM '65 Proceedings of the 1965 20th national conference
Design verification of large scientific computers
DAC '77 Proceedings of the 14th Design Automation Conference
Developments in computer simulation of gate level physical logic
DAC '79 Proceedings of the 16th Design Automation Conference
Hardware acceleration of logic simulation using a data flow microarchitecture
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
A fast signature simulation tool for built-in self-testing circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Clock even suppression algorithm of VELVET and its application to S-820 development
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Modeling switch-level simulation using data flow
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
DAC '82 Proceedings of the 19th Design Automation Conference
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Execution speed of event driven simulators can be enhanced by software designs that use vector coding techniques developed for scientific processing. The power of vector coding can be utilized by logic simulators running on scalar processors.