A fast signature simulation tool for built-in self-testing circuits

Authors:
S. B. Tan;K. Totton;K. Baker;P. Varma;R. Porter
Affiliations:
GEC Research Limited, Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom;British Telecom Research Laboratories, UK;GEC Research Limited, Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom;GEC Research Limited, Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom;GEC Research Limited, Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP, United Kingdom
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

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Abstract

This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input and produces C code simulation modules comprising Boolean relations that represent the structure of the circuit. These C code modules are then compiled and linked together to form the basis of the compiled code simulator. Simulation is invoked by executing the compiled C code description of the circuit. The simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations Per Second (GEPS) have been achieved using the FSS.