SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A fast signature simulation tool for built-in self-testing circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Demand driven simulation: BACKSIM
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
An automated method for designing logic circuit diagnostic programs
DAC '71 Proceedings of the 8th Design Automation Workshop
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST
IEEE Transactions on Computers
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A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.