Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms
Integration, the VLSI Journal
IEEE Design & Test
Reducing Hardware with Fuzzy Multiple Signature Analysis
IEEE Design & Test
Built-in Self Test Based on Multiple On-Chip Signature Checking
Journal of Electronic Testing: Theory and Applications
Reducing Hardware with Fuzzy Multiple Signature Analysis
IEEE Design & Test
A Low-Cost Concurrent BIST Scheme for Increased Dependability
IEEE Transactions on Dependable and Secure Computing
| Hi-index | 14.98 |
Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propose a novel multiple intermediate signature analysis scheme which checks n signatures against a single reference, thus making the circuitry for checking n signatures essentially the same as that for checking only one. The cost for implementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. This paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identical signatures at arbitrary check points for all circuits.