Built-in Self Test Based on Multiple On-Chip Signature Checking

Authors:
Mohammed Fadle Abdulla;C. P. Ravikumar;Anshul Kumar
Affiliations:
Department of Electrical and Electronic Engineering, Faculty of Engineering, University of Aden, Yemen. mohammed_abdulla@hotmail.com;Department of Electrical Engineering, Indian Institute of Technology, New Delhi, 110016, India. rkumar@ee.iitd.ernet.in;Department of Computer Science & Engineering, Indian Institute of Technology, New Delhi, 110016, India. anshul@cse.iitd.ernet.in
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
1999

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Abstract

We propose an improved BIST architecture which supports on-chipcomparison of signatures at no significant increase in area. Theproposed test architecture reduces detection latency and eliminatesthe lengthy scan-out phase from each test session by allowing testingand on-chip signature comparison of multiple intermediate signaturesto occur concurrently. The work is based on a novel procedure toimplement the multiple on-chip signature checking. We show that sucha test method gives significant improvements in test application timeand aliasing probability. This paper also presented two techniquesto minimize the test area overhead with a very small test timeoverhead compare to the conventional schemes. These techniquesresulted in up to 80% savings in test area overhead for someHigh-level synthesis benchmark circuits. This paper also presents analiasing analysis of the proposed scheme.