The tea-leaf reader algorithm: an efficient implementation of CRC-16 and CRC-32
Communications of the ACM
A fast signature simulation tool for built-in self-testing circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Computation of cyclic redundancy checks via table look-up
Communications of the ACM
An Efficient Signature Computation Method
IEEE Design & Test
Fast Signature Computation for Linear Compactors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fast computation of C-MISR signatures
ATS '95 Proceedings of the 4th Asian Test Symposium
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Signature analyzers are widely used for compressing test responses. Off-line determination of signatures (for both good circuit and faulty circuits) is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we investigate techniques for speeding up the simulation of multi-input signature registers (MISRs). We first analyze a speedup technique that processes each input independently by table lookups, and show its shortcomings. We then propose a speedup technique that converts the MISR into an equivalent single input circuit. We also present the results of a simulation study that show that this technique achieves a good speedup.