The tea-leaf reader algorithm: an efficient implementation of CRC-16 and CRC-32
Communications of the ACM
A fast signature simulation tool for built-in self-testing circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Computation of cyclic redundancy checks via table look-up
Communications of the ACM
Fast Signature Computation for Linear Compactors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fast computation of MISR signatures
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
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A signature generation algorithm for linear-feedback shift register (LFSR)-based compactors used in fault simulation of built-in self-test digital circuits is presented. The algorithm uses small- to medium-size lookup tables to generate signatures for internal as well as external exclusive-OR LFSRs of any length. The basic concept can be extended to general linear compactors. Algorithms that convert signatures from one form of LFSR to the other are also presented.