Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Clock even suppression algorithm of VELVET and its application to S-820 development
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Comparing Layouts with HDL Models: A Formal Verification Technique
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
Periodic signal suppression in a concurrent fault simulator
EURO-DAC '91 Proceedings of the conference on European design automation
Formal specification and verification of a dataflow processor array
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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