Test pattern generation for sequential MOS circuits by symbolic fault simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Analysis of switch-level faults by symbolic simulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An algorithm for incremental timing analysis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Incremental-in-time algorithm for digital simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Synthesis of 100-percent Testable Logic Networks
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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Incremental methods are successfully applied to deal with successive verifications of slightly modified switch-level networks. That is, only those parts affected by the changes are symbolically traversed for verification. In this paper, we present an incremental technique for symbolic simulators which is inspired in both existing incremental techniques for non-symbolic simulators and a token-passing mechanisms in Petri nets.