Logical Design of Digital Systems
Logical Design of Digital Systems
Thor user''s manual: tutorial and commands
Thor user''s manual: tutorial and commands
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Incremental circuit simulation using waveform relaxation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Zero delay versus positive delay in an incremental switch-level simulator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Parallel algorithms for the circuit value update problem
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Proceedings of the conference on Design, automation and test in Europe
Updateable simulation of communication networks
Proceedings of the sixteenth workshop on Parallel and distributed simulation
Run-time consistency checking in discrete simulation models
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Time-Parallel Trace-Driven Simulation of CSMA/CD
Proceedings of the seventeenth workshop on Parallel and distributed simulation
Incremental switch-level simulation with zero/integer-delay
EURO-DAC '91 Proceedings of the conference on European design automation
Parallel Algorithms for the Circuit Value Update Problem
Theory of Computing Systems
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Recently, an incremental algorithm (incremental-in-space algorithm) for digital simulation has been studied with good results in speeding up simulation. In this paper we present another algorithm (incremental-in-time algorithm) for incremental simulation of digital circuits. The incremental-in-space algorithm pessimistically resimulates the circuit components that could be affected by design changes throughout the simulation time frames. On the other hand, the incremental-in-time algorithm resimulates a circuit component only for the simulation time frames when its inputs or internal state variables make different state transitions from the previous simulation run. It maximally utilizes the past history thereby reducing the number of component evaluations to a minimum. Experimental results obtained for several practical circuits show speedups up to 30 times faster than conventional event-driven simulation.