Parallel Algorithms for the Circuit Value Update Problem

  • Authors:

  • C. E. Leiserson;K. H. Randall

  • Affiliations:

  • Laboratory for Computer Science, MIT, 545 Technology Square, Cambridge, MA 02139, USA cel@mit.edu/ randall@theory.lcs.mit.edu, US;Laboratory for Computer Science, MIT, 545 Technology Square, Cambridge, MA 02139, USA cel@mit.edu/ randall@theory.lcs.mit.edu, US

  • Venue:
  • Theory of Computing Systems
  • Year:
  • 1997

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Abstract

The circuit value update problem is the problem of updating values in a representation of a combinational circuit when some of the inputs are changed. We assume for simplicity that each combinational element has bounded fan-in and fan-out and can be evaluated in constant time. This problem is easily solved on an ordinary serial computer in O(W+D) time, where W is the number of elements in the altered subcircuit and D is the subcircuit's embedded depth (its depth measured in the original circuit).In this paper we show how to solve the circuit value update problem efficiently on a P-processor parallel computer. We give a straightforward synchronous, parallel algorithm that runs in $O(W/P + D\lg P)$ expected time. Our main contribution, however, is an optimistic, asynchronous, parallel algorithm that runs in $O(W/P+D+\lg W + \lg P)$ expected time, where W and D are the size and embedded depth, respectively, of the ``volatile'' subcircuit, the subcircuit of elements that have inputs which either change or glitch as a result of the update. To our knowledge, our analysis provides the first analytical bounds on the running time of an optimistic, asynchronous, parallel algorithm.