IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Incremental approach to digital simulation
Incremental approach to digital simulation
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
Incremental-in-time algorithm for digital simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Incremental vlsi design systems based on circular attribute grammars (fixed point computation, computer aided design)
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We present the methods used in the implementation of an incremental zero/integer--delay switch--level logic simulator for MOS circuits based on the MOSSIM II switch--level model. Zero--delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer--delay timing, a generalization of unit--delay methods, provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a fully-integrated capture--compile--simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit.