A design verification methodology based on concurrent simulation and clock suppression
DAC '83 Proceedings of the 20th Design Automation Conference
Speed and accuracy in digital network simulation based on structural modeling
DAC '82 Proceedings of the 19th Design Automation Conference
Automatic clock abstraction from sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A hardware-software co-simulator for embedded system design and debugging
Readings in hardware/software co-design
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Clock suppression has been proposed to take advantage of the periodic signals such as the clock present in synchronous designs. In clock suppression, no events due to the clock input are generated, but the information can be reconstructed as needed. In this paper, we present periodic signal suppression, which is a generalized form of clock suppression, as a means to suppress predictable events of all periodic signals throughout the circuit. To do this, a special signal state labeled P is introduced. P states indicate that signals are periodic, but cause no unnecessary activity in an event driven simulator. At any time, the original waveform can be reconstructed from the periodic signal. Our general implementation allows clock suppression to work on divided or gated clocks and on signals that may alternate periodic and non-periodic behavior in addition to the clock tree. Moreover, concurrent simulation of faults on the suppressed signal wires including the clock tree is possible.