Comparing Layouts with HDL Models: A Formal Verification Technique

State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis

EURO-DAC '92 Proceedings of the conference on European design automation

Verity—a formal verification program for custom CMOS circuits

IBM Journal of Research and Development - Special issue: IBM CMOS technology

Automatic clock abstraction from sequential circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

The maximal VHDL subset with a cycle-level abstraction

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Verifying real-time properties of MOS-transistor circuits

EDTC '95 Proceedings of the 1995 European conference on Design and Test