Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Applications of temporal logic to the specification of real time systems (extended abstract)
Proceedings of a Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Handbook of theoretical computer science (vol. B)
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Verification of asynchronous interface circuits with bounded wire delays
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
"Sometime" is sometimes "not never": on the temporal logic of programs
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Comparing Layouts with HDL Models: A Formal Verification Technique
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Efficient Algorithm for Real-Time Symbolic Model Checking
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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A verification approach which allows the verification of functional and timing behavior of circuits at transistor level is presented. It is aimed at the verification of asynchronous interfaces and standard-cell library modules. In contrast to other approaches, timing is explicitly considered, allowing one to verify timing-dependent effects with a high degree of accuracy. To conveniently specify desired properties, a specification language based on Linear Quantized Temporal Logic (QLTL) is provided. For an efficient verification, input constraints, necessary for a proper circuit functioning, are converted into input constraining automata, reducing the reachable state space and providing a model linearisation, necessary to prove linear QLTL formulas by branching CTL model checking.