Methodology for & results from the use of a hardware logic simulation engine for fault simulation

Authors:
Leslie Turner Smith;Roy R. Rezac
Affiliations:
Digital Equipment Corporation, Hudson, Massachusetts;Digital Equipment Corporation, Hudson, Massachusetts
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

Software fault simulation programs. whether serial. parallel. deductive or concurrent. have been the accepted approach for grading test patterns or qualifying diagnostic programs. With the advent of hardware simulation engines. a potentially faster method of doing fault simulation has arisen. This paper reports on a new methodology for the use of both a hardware simulation engine and a concurrent software simulator to assist in verifying hardware diagnostic programs.